Data access operations commonly require copying data from non-sequential source memory areas to a single, sequential destination memory area, to be used by a requesting process. Such operations may involve multiple, separate Direct Memory Access (DMA) transactions, to access different, non-sequential addresses of the source memory. The latency of non-sequential data access operations increases with the data storage entropy (e.g. the extent to which the data is non-sequential), as all copy operations must be completed before the data itself can be used by the requesting process.
Accessing non-sequential data on the source memory will normally include the steps of: (1) Copying each data unit separately, using a separate DMA transaction; (2) Polling for all DMA transactions to be completed; and (3) Enabling another process to access the source memory only after all the data of the previous process has been read. This work flow may be unacceptable in latency-sensitive applications.
In typical cases, the data itself may be used in a sequential manner (e.g. the data which is copied by the first DMA transaction may be used first by the requesting process). However, this quality is difficult to exploit in order to pipeline the DMA transactions with the requesting process itself. Typically, pipelining the requesting process with the DMA transactions requires dividing the requesting process into multiple sub-processes, each waiting for its own DMA transaction to be completed. This architecture requires a multiple polling scheme: both on the DMA transaction, and on the sub-process which makes use of the copied data, each waiting for the other to be completed.
Accordingly, a system and a method for dynamic pipelining of DMA transactions is desirable.